Typical integrated memory devices include arrays of memory cells arranged in rows and columns. In many such memory devices, several redundant rows and columns are provided to replace malfunctioning memory cells found during testing. Testing is typically performed by having predetermined data values written to selected row and column addresses that correspond to memory cells. The memory cells are then read to determine if the data read matches the data written to those memory cells. If the read data does not match the written data, then those memory cells are likely to contain defects which will prevent proper operation of the memory device.
The defective memory cells may be replaced by enabling the redundant circuitry. A malfunctioning memory cell in a column or a row is substituted with a corresponding redundant element, such as an entire column or row of redundant memory cells, respectively. Therefore, a memory device need not be discarded even though it contains defective memory cells. Substitution of one of the redundant rows or columns is accomplished in a memory device by programming a specific combination of fuses, or if the memory device uses antifuses, by programming a specific combination of antifuses, located in one of several fuse or antifuse circuits in the memory device. Conventional fuses are resistive devices which may be opened or broken with a laser beam or an electric current. Antifuses are capacitive devices that may be closed or blown by breaking down a dielectric layer in the antifuse with a relatively high voltage. A set of fuses or antifuses is associated with each redundant element, and is programmed, or “blown,” according to the address of the defective element the redundant element will replace. The programmed addresses for the defective memory locations that are mapped to a redundant element are static, that is, once programmed, the address of the defective memory locations are known well before a row or a column of memory of the memory is ever accessed.
When a row or column address received by the memory device matches one of the programmed addresses, the redundant element associated with the matching address is accessed instead of the row or column having the defective memory cells. In determining whether an address the memory device receives matches one of the programmed addresses, each incoming address is compared to the addresses programmed in the fuse or antifuse circuits. If a match is detected, then the corresponding redundant row or column is accessed, and the defective row or column is ignored, thus, remapping the memory address to the redundant element.
FIG. 1 is a block diagram for a conventional redundancy system 100 that can be used for row redundancy elements or for column redundancy elements, as previously described. As shown in FIG. 1, there are “n” normal memory elements and “m” redundant elements. Memory addresses are provided to an address predecoder 104 and to m comparators 108(1)–108(m). Each of the comparators 108(1)–108(m) further receives a respective redundancy address against which the memory addresses are compared. Redundancy addresses are provided by a respective antifuse circuit (not shown) in which the memory address for a defective memory is programmed.
In operation, memory addresses corresponding to memory locations for memory access operations are provided to the memory device. The address predecoder 104 generates internal predecoded address signals AXY<i>, “i” representing an integer value corresponding to the number of internal predecoded address signals are generated, that are provided to n decoders 120(1)–120(n) through a delay 110. As will be explained in more detail below, the delay 110 provides sufficient delay to the AXY<i> signals to allow for the decoders 120(1)–120(m) to be disabled when the memory address does match one of the programmed addresses provided to one of the comparators 108(1)–108(m). In response to the AXY<i> signals, one of the decoders 120(1)–120(n) generates an active decode signal DEC(1)–DEC(n) to enable a respective driver 130(1)–130(n) to generate a respective selection signal CSELn activating one of the n normal elements to be accessed. As previously discussed, the memory address is also compared by the comparators 108(1)–108(m) to the respective redundancy addresses. If a memory address received by the memory device does not match any of the redundancy addresses provided to the comparators 108(1)–108(m), none of the comparators will generate an active redundancy match signal RED.
In contrast, if a memory address matches one of the programmed redundancy addresses provided to the comparators 108(1)–108(m), the comparator that determines the match generates an active REDm signal. The RED(1)–RED(m) signals, including the active REDm signal, are provided to a respective redundancy decoder 124(1)–124(m) through a respective delay 112(1)–112(m). The delays 112(1)–112(m) are generally the same as the delay 110 in terms of delay time. The redundancy decoders 124(1)–124(m) included in the signal path to match the propagation delay of the decoders 120(1)–120(n). The redundancy decoder 124(1)–124(m) that receives the active RED(1)–RED(m) signal generates an active redundancy enable signal RENABLEm to enable a respective redundancy driver 134(1)–134(m). In turn, the redundancy driver 134(1)–134(m) that is enabled generates a redundancy selection signal RCSELm to activate the respective redundant element.
While one of the comparators generates an active REDm signal to activate the respective redundant element, the address predecoder 104 is also going through the process of generating AXY<i> signals to access the normal memory element corresponding to the memory address. In order to prevent the decoder 120(1)–120(n) corresponding to the memory address from activating the respective driver 130(1)–130(n), and the redundancy decoder 124(1)–124(m) corresponding to the comparator 108(1)–108(m) determining the matching address from activating the respective redundancy driver 134(1)–134(m) at the same time, the logic circuit 116 generates an active decoder disable signal DISABLE in response to any one of the RED(1)–RED(m) signals being active. The DISABLE signal is provided to all of the decoders 120(1)–120(n) to prevent any of the decoders from activating the respective driver. The delay 110 adds sufficient delay time to the propagation of the AXY<i> signals to accommodate the propagation delay through the comparators 108(1)–108(m) and the logic circuit 116. Thus, the decoders 120(1)–120(n) will be disabled by the active DISABLE signal before the AXY<i> signals reach the decoders 120(1)–120(n).
FIG. 2 is a timing diagram of various signals during the operation of the redundancy system 100 of FIG. 1. At a time T1, the memory address transitions indicating a new memory address has been provided to the address predecoder 104 and the comparators 108(1)–108(m). At a time T2, a predecode propagation delay tPRE after the time T1, the address predecoder 104 generates the AXY<i> signals and the comparators 108(1)–108(m) generate the RED(1)–RED(m) signals. At a time T3, dAXY<i> signals and dRED(1)–dRED(m) signals are output by the delay 110 and the delays 112(1)–112(m) in response to the AXY<i> signals and RED(1)–RED(m) signals, all respectively. As previously discussed, the delays 110 and 112(1)–112(m) are provided to accommodate the propagation delay tDIS for generating an active DISABLE signal if a redundancy element is being accessed instead of the normal element. Without the delays 110 and 112(1)–112(m), the AXY<i> signals and the RED(1)–RED(m) signals would be provided to the decoders 120(1)–120(n) and the 124(1)–124(m) before the DISABLE signal could be provided to disable the decoders 120(1)–120(n) in the event a redundancy element is being accessed. Thus, the time between T2 and T3 is roughly equal to the propagation delay time tDIS, which can be approximately equal to or greater than the propagation delay of the logic circuit 116 to ensure that the decoders 120(1)–120(n) are disabled before they can be activated if a redundancy element is to be accessed.
As shown in FIG. 2, at a time T4, which is a decoder propagation delay tDEC after the time T3, the dAXY<i> signals have been provided to the decoders 120(1)–120(n), and one of the decoders 120(1)–120(n) will generate an active DEC(1)–DEC(n) signal to enable one of the drivers 130(1)–130(n), unless an active DISABLE has been provided to disable the decoders 120(1)–120(n). Similarly, if an address match is detected by one of the comparators 108(1)–108(m), at the time T4 the dRED(1)–dRED(m) signals have been provided to the redundancy decoder 124(1)–124(m) corresponding to the comparator 108(1)–108(m) detecting the matching addresses and that redundancy decoder 124(1)–124(m) is ready to generate an active RENABLEm signal. Finally at a time T5, a driver propagation delay tDRV after the time T4, the select signal CSEL(1)–CSEL(n) (to access a normal element) or RCSEL(1)–RCSEL(m) (to access a redundant element rather than the defective normal element) is generated to activate one of the normal or redundant elements. As shown in the timing diagram of FIG. 2, and as previously described, the delay time tD is added in the conventional redundancy system 100 regardless of whether a redundant element is accessed or a normal element is accessed. The tD of the conventional redundancy system 100 directly affects the access time of a memory device, that is, the time for data to be read from a memory device. Consequently, avoiding the delay time tD to improve access time for the memory devices is desirable.
One approach that has been developed to avoid the tD of the conventional redundancy system 100 is to include dedicated disable logic for each row or column of normal memory. The disable logic can be programmed through the use of antifuses at the same time redundancy addresses are being programmed into the antifuse circuits for the redundant elements. Defective rows or columns of memory can be disabled by programming the disable logic dedicated for that row or column of memory. As a result, when the memory device receives a memory address corresponding to one of the defective rows or columns of memory, there is no need to wait for signals to propagate through a comparator or a logic circuit to disable access to the defective row or column since the dedicated disable logic has already disabled the defective row or column. Although including the dedicated disable logic eliminates the need to include a delay time tD in the signal paths to access normal and redundant elements, having dedicated disable logic for each row or column of memory in a memory device consumes a considerable amount of space on the semiconductor die of the memory device. Additionally, the use of antifuses or fuses to program the dedicated disable logic further exacerbates the problem since the physical dimensions of the antifuses and fuses also require considerable space on the die. Thus, the use of dedicated disable logic for the rows or columns of memory is not practical.
Another redundancy system that has been developed to reduce or eliminate the delay time tD utilizes redundant elements physically located at the periphery of a redundancy domain that are utilized by “shifting” the decoding of memory addresses “up” or “down” to avoid defective memory elements. A redundancy domain includes a limited number of redundancy elements allocated for the defective memory of a region of memory. For example, with respect to column redundancy, when a defective column of memory is identified, the defective column is ignored by shifting all of the column addresses over by one column, and utilizing a column of redundant memory at the periphery. Thus, the address of the defective column is now remapped to an adjacent column of memory. Shortcomings of this redundancy system include sacrificing considerable space on the die of the memory device to include the logic circuits necessary to remap the shifted memory addresses. Additionally, this redundancy system lacks flexibility because the allocation of redundant elements for each redundancy domain is limited by the complexity of the supporting logic. Moreover, there is potential access time penalties caused by the propagation delay of signals through the supporting logic.
Therefore, there is a need for an alternative redundancy system that reduces or eliminates the forced delay of conventional redundancy systems and that can be practically implemented.